Maxim DS5001FP Specifiche

1 of 25 REV: 072806 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revis

DS5002FP Secure Microprocessor Chip 10 of 25 Figure 7. RPC Timing Mode

DS5002FP Secure Microprocessor Chip 11 of 25 PIN DESCRIPTION PIN NAME FUNCTION 11, 9, 7, 5, 1, 79, 77, 75 P0.0–P0.7 General-Purpose I/O Port 0. Th

DS5002FP Secure Microprocessor Chip 12 of 25 PIN NAME FUNCTION 62 CE4 Active-Low Chip Enable 4. This chip enable is provided to access a fourth 32

DS5002FP Secure Microprocessor Chip 13 of 25 DETAILED DESCRIPTION The DS5002FP implements a security system that is an improved version of its pred

DS5002FP Secure Microprocessor Chip 14 of 25 Figure 8. Block Diagram

DS5002FP Secure Microprocessor Chip 15 of 25 SECURE OPERATION OVERVIEW The DS5002FP incorporates encryption of the activity on its byte-wide addres

DS5002FP Secure Microprocessor Chip 16 of 25 Figure 9. Security Circuitry The address encryptor translates each “logical” address, i.e., the n

DS5002FP Secure Microprocessor Chip 17 of 25 protection measure, the address encryptor also generates “dummy” read access cycles whenever time is a

DS5002FP Secure Microprocessor Chip 18 of 25 observe such relationships. Although it is very unlikely that an application program could be decipher

DS5002FP Secure Microprocessor Chip 19 of 25 Table 1. Serial Bootstrap Loader Commands COMMAND FUNCTION C Return CRC-16 of the program/data NV RA

DS5002FP Secure Microprocessor Chip 2 of 25 ELECTRICAL SPECIFICATIONS The DS5002FP adheres to all AC and DC electrical specifications published for

DS5002FP Secure Microprocessor Chip 20 of 25 selections are made using special function registers. The memory map and its controls are covered in d

DS5002FP Secure Microprocessor Chip 21 of 25 Figure 11. Memory Map In Partitionable Mode (PM = 0) Figure 12. Memory Map with PES = 1

DS5002FP Secure Microprocessor Chip 22 of 25 Figure 13 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this c

DS5002FP Secure Microprocessor Chip 23 of 25 Figure 14. Connection to 64k x 8 SRAM POWER MANAGEMENT The DS5002FP monitors VCC to provide power-

DS5002FP Secure Microprocessor Chip 24 of 25 SELECTOR GUIDE STANDARD PART Pb-FREE/RoHS COMPLIANT TEMP RANGE MAX CLOCK SPEED (MHz) INTERNAL MICROPRO

DS5002FP Secure Microprocessor Chip 25 of 25 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry e

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DS5002FP Secure Microprocessor Chip 3 of 3 DC CHARACTERISTICS (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.)** PARAMETER SYMBOL CONDITIONS MIN TYP

DS5002FP Secure Microprocessor Chip 4 of 25 AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure

DS5002FP Secure Microprocessor Chip 5 of 25 Figure 2. Expanded Data Memory Write Cycle AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE (VCC = 5V ± 10

DS5002FP Secure Microprocessor Chip 6 of 25 AC CHARACTERISTICS—POWER CYCLE TIME (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 4) # PARAMETER SYMBOL M

DS5002FP Secure Microprocessor Chip 7 of 25 AC CHARACTERISTICS—SERIAL PORT TIMING, MODE 0 (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 5) # PARAMETE

DS5002FP Secure Microprocessor Chip 8 of 25 AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 6) # P

DS5002FP Secure Microprocessor Chip 9 of 25 RPC AC CHARACTERISTICS, DBB READ (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7) # PARAMETER SYMBOL MIN