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DS5002FP Secure Microprocessor Chip

22 of 25

Figure 13

illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration,

both program and data are stored in a common RAM chip. Figure 14

shows a similar system with using two 32kB

SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus

connects the data I/O lines of the SRAM.

Figure 13. Connection to 128k x 8 SRAM

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Maxim DS5001FP Specifiche Pagina 22